
radix:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400558 <_init>:
  400558:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40055c:	910003fd 	mov	x29, sp
  400560:	9400003a 	bl	400648 <call_weak_fn>
  400564:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400568:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400570 <.plt>:
  400570:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400574:	90000090 	adrp	x16, 410000 <__FRAME_END__+0xf3cc>
  400578:	f947fe11 	ldr	x17, [x16, #4088]
  40057c:	913fe210 	add	x16, x16, #0xff8
  400580:	d61f0220 	br	x17
  400584:	d503201f 	nop
  400588:	d503201f 	nop
  40058c:	d503201f 	nop

0000000000400590 <__libc_start_main@plt>:
  400590:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400594:	f9400211 	ldr	x17, [x16]
  400598:	91000210 	add	x16, x16, #0x0
  40059c:	d61f0220 	br	x17

00000000004005a0 <memset@plt>:
  4005a0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4005a4:	f9400611 	ldr	x17, [x16, #8]
  4005a8:	91002210 	add	x16, x16, #0x8
  4005ac:	d61f0220 	br	x17

00000000004005b0 <__gmon_start__@plt>:
  4005b0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4005b4:	f9400a11 	ldr	x17, [x16, #16]
  4005b8:	91004210 	add	x16, x16, #0x10
  4005bc:	d61f0220 	br	x17

00000000004005c0 <abort@plt>:
  4005c0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4005c4:	f9400e11 	ldr	x17, [x16, #24]
  4005c8:	91006210 	add	x16, x16, #0x18
  4005cc:	d61f0220 	br	x17

00000000004005d0 <pow@plt>:
  4005d0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4005d4:	f9401211 	ldr	x17, [x16, #32]
  4005d8:	91008210 	add	x16, x16, #0x20
  4005dc:	d61f0220 	br	x17

00000000004005e0 <printf@plt>:
  4005e0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4005e4:	f9401611 	ldr	x17, [x16, #40]
  4005e8:	9100a210 	add	x16, x16, #0x28
  4005ec:	d61f0220 	br	x17

00000000004005f0 <putchar@plt>:
  4005f0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4005f4:	f9401a11 	ldr	x17, [x16, #48]
  4005f8:	9100c210 	add	x16, x16, #0x30
  4005fc:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400600 <_start>:
  400600:	d280001d 	mov	x29, #0x0                   	// #0
  400604:	d280001e 	mov	x30, #0x0                   	// #0
  400608:	aa0003e5 	mov	x5, x0
  40060c:	f94003e1 	ldr	x1, [sp]
  400610:	910023e2 	add	x2, sp, #0x8
  400614:	910003e6 	mov	x6, sp
  400618:	580000c0 	ldr	x0, 400630 <_start+0x30>
  40061c:	580000e3 	ldr	x3, 400638 <_start+0x38>
  400620:	58000104 	ldr	x4, 400640 <_start+0x40>
  400624:	97ffffdb 	bl	400590 <__libc_start_main@plt>
  400628:	97ffffe6 	bl	4005c0 <abort@plt>
  40062c:	00000000 	.inst	0x00000000 ; undefined
  400630:	00400aa8 	.word	0x00400aa8
  400634:	00000000 	.word	0x00000000
  400638:	00400b50 	.word	0x00400b50
  40063c:	00000000 	.word	0x00000000
  400640:	00400bd0 	.word	0x00400bd0
  400644:	00000000 	.word	0x00000000

0000000000400648 <call_weak_fn>:
  400648:	90000080 	adrp	x0, 410000 <__FRAME_END__+0xf3cc>
  40064c:	f947f000 	ldr	x0, [x0, #4064]
  400650:	b4000040 	cbz	x0, 400658 <call_weak_fn+0x10>
  400654:	17ffffd7 	b	4005b0 <__gmon_start__@plt>
  400658:	d65f03c0 	ret
  40065c:	00000000 	.inst	0x00000000 ; undefined

0000000000400660 <deregister_tm_clones>:
  400660:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400664:	91012000 	add	x0, x0, #0x48
  400668:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  40066c:	91012021 	add	x1, x1, #0x48
  400670:	eb00003f 	cmp	x1, x0
  400674:	540000a0 	b.eq	400688 <deregister_tm_clones+0x28>  // b.none
  400678:	90000001 	adrp	x1, 400000 <_init-0x558>
  40067c:	f945f821 	ldr	x1, [x1, #3056]
  400680:	b4000041 	cbz	x1, 400688 <deregister_tm_clones+0x28>
  400684:	d61f0020 	br	x1
  400688:	d65f03c0 	ret
  40068c:	d503201f 	nop

0000000000400690 <register_tm_clones>:
  400690:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400694:	91012000 	add	x0, x0, #0x48
  400698:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  40069c:	91012021 	add	x1, x1, #0x48
  4006a0:	cb000021 	sub	x1, x1, x0
  4006a4:	9343fc21 	asr	x1, x1, #3
  4006a8:	8b41fc21 	add	x1, x1, x1, lsr #63
  4006ac:	9341fc21 	asr	x1, x1, #1
  4006b0:	b40000a1 	cbz	x1, 4006c4 <register_tm_clones+0x34>
  4006b4:	90000002 	adrp	x2, 400000 <_init-0x558>
  4006b8:	f945fc42 	ldr	x2, [x2, #3064]
  4006bc:	b4000042 	cbz	x2, 4006c4 <register_tm_clones+0x34>
  4006c0:	d61f0040 	br	x2
  4006c4:	d65f03c0 	ret

00000000004006c8 <__do_global_dtors_aux>:
  4006c8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4006cc:	910003fd 	mov	x29, sp
  4006d0:	f9000bf3 	str	x19, [sp, #16]
  4006d4:	b0000093 	adrp	x19, 411000 <__libc_start_main@GLIBC_2.17>
  4006d8:	39412260 	ldrb	w0, [x19, #72]
  4006dc:	35000080 	cbnz	w0, 4006ec <__do_global_dtors_aux+0x24>
  4006e0:	97ffffe0 	bl	400660 <deregister_tm_clones>
  4006e4:	52800020 	mov	w0, #0x1                   	// #1
  4006e8:	39012260 	strb	w0, [x19, #72]
  4006ec:	f9400bf3 	ldr	x19, [sp, #16]
  4006f0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4006f4:	d65f03c0 	ret

00000000004006f8 <frame_dummy>:
  4006f8:	17ffffe6 	b	400690 <register_tm_clones>

00000000004006fc <getLoopTimes>:
  4006fc:	d10083ff 	sub	sp, sp, #0x20
  400700:	b9000fe0 	str	w0, [sp, #12]
  400704:	52800020 	mov	w0, #0x1                   	// #1
  400708:	b9001fe0 	str	w0, [sp, #28]
  40070c:	b9400fe0 	ldr	w0, [sp, #12]
  400710:	528ccce1 	mov	w1, #0x6667                	// #26215
  400714:	72acccc1 	movk	w1, #0x6666, lsl #16
  400718:	9b217c01 	smull	x1, w0, w1
  40071c:	d360fc21 	lsr	x1, x1, #32
  400720:	13027c21 	asr	w1, w1, #2
  400724:	131f7c00 	asr	w0, w0, #31
  400728:	4b000020 	sub	w0, w1, w0
  40072c:	b9001be0 	str	w0, [sp, #24]
  400730:	1400000d 	b	400764 <getLoopTimes+0x68>
  400734:	b9401fe0 	ldr	w0, [sp, #28]
  400738:	11000400 	add	w0, w0, #0x1
  40073c:	b9001fe0 	str	w0, [sp, #28]
  400740:	b9401be0 	ldr	w0, [sp, #24]
  400744:	528ccce1 	mov	w1, #0x6667                	// #26215
  400748:	72acccc1 	movk	w1, #0x6666, lsl #16
  40074c:	9b217c01 	smull	x1, w0, w1
  400750:	d360fc21 	lsr	x1, x1, #32
  400754:	13027c21 	asr	w1, w1, #2
  400758:	131f7c00 	asr	w0, w0, #31
  40075c:	4b000020 	sub	w0, w1, w0
  400760:	b9001be0 	str	w0, [sp, #24]
  400764:	b9401be0 	ldr	w0, [sp, #24]
  400768:	7100001f 	cmp	w0, #0x0
  40076c:	54fffe41 	b.ne	400734 <getLoopTimes+0x38>  // b.any
  400770:	b9401fe0 	ldr	w0, [sp, #28]
  400774:	910083ff 	add	sp, sp, #0x20
  400778:	d65f03c0 	ret

000000000040077c <findMaxNum>:
  40077c:	d10083ff 	sub	sp, sp, #0x20
  400780:	f90007e0 	str	x0, [sp, #8]
  400784:	b90007e1 	str	w1, [sp, #4]
  400788:	b9001bff 	str	wzr, [sp, #24]
  40078c:	b9001fff 	str	wzr, [sp, #28]
  400790:	14000012 	b	4007d8 <findMaxNum+0x5c>
  400794:	b9801fe0 	ldrsw	x0, [sp, #28]
  400798:	d37ef400 	lsl	x0, x0, #2
  40079c:	f94007e1 	ldr	x1, [sp, #8]
  4007a0:	8b000020 	add	x0, x1, x0
  4007a4:	b9400000 	ldr	w0, [x0]
  4007a8:	b9401be1 	ldr	w1, [sp, #24]
  4007ac:	6b00003f 	cmp	w1, w0
  4007b0:	540000ea 	b.ge	4007cc <findMaxNum+0x50>  // b.tcont
  4007b4:	b9801fe0 	ldrsw	x0, [sp, #28]
  4007b8:	d37ef400 	lsl	x0, x0, #2
  4007bc:	f94007e1 	ldr	x1, [sp, #8]
  4007c0:	8b000020 	add	x0, x1, x0
  4007c4:	b9400000 	ldr	w0, [x0]
  4007c8:	b9001be0 	str	w0, [sp, #24]
  4007cc:	b9401fe0 	ldr	w0, [sp, #28]
  4007d0:	11000400 	add	w0, w0, #0x1
  4007d4:	b9001fe0 	str	w0, [sp, #28]
  4007d8:	b9401fe1 	ldr	w1, [sp, #28]
  4007dc:	b94007e0 	ldr	w0, [sp, #4]
  4007e0:	6b00003f 	cmp	w1, w0
  4007e4:	54fffd8b 	b.lt	400794 <findMaxNum+0x18>  // b.tstop
  4007e8:	b9401be0 	ldr	w0, [sp, #24]
  4007ec:	910083ff 	add	sp, sp, #0x20
  4007f0:	d65f03c0 	ret

00000000004007f4 <sort2>:
  4007f4:	d10d83ff 	sub	sp, sp, #0x360
  4007f8:	a9007bfd 	stp	x29, x30, [sp]
  4007fc:	910003fd 	mov	x29, sp
  400800:	f9000fa0 	str	x0, [x29, #24]
  400804:	b90017a1 	str	w1, [x29, #20]
  400808:	b90013a2 	str	w2, [x29, #16]
  40080c:	9100a3a0 	add	x0, x29, #0x28
  400810:	d2806401 	mov	x1, #0x320                 	// #800
  400814:	aa0103e2 	mov	x2, x1
  400818:	52800001 	mov	w1, #0x0                   	// #0
  40081c:	97ffff61 	bl	4005a0 <memset@plt>
  400820:	b94013a0 	ldr	w0, [x29, #16]
  400824:	51000400 	sub	w0, w0, #0x1
  400828:	1e620000 	scvtf	d0, w0
  40082c:	1e604001 	fmov	d1, d0
  400830:	1e649000 	fmov	d0, #1.000000000000000000e+01
  400834:	97ffff67 	bl	4005d0 <pow@plt>
  400838:	1e780000 	fcvtzs	w0, d0
  40083c:	b90353a0 	str	w0, [x29, #848]
  400840:	b9035fbf 	str	wzr, [x29, #860]
  400844:	1400003c 	b	400934 <sort2+0x140>
  400848:	b9835fa0 	ldrsw	x0, [x29, #860]
  40084c:	d37ef400 	lsl	x0, x0, #2
  400850:	f9400fa1 	ldr	x1, [x29, #24]
  400854:	8b000020 	add	x0, x1, x0
  400858:	b9400001 	ldr	w1, [x0]
  40085c:	b94353a0 	ldr	w0, [x29, #848]
  400860:	1ac00c21 	sdiv	w1, w1, w0
  400864:	528ccce0 	mov	w0, #0x6667                	// #26215
  400868:	72acccc0 	movk	w0, #0x6666, lsl #16
  40086c:	9b207c20 	smull	x0, w1, w0
  400870:	d360fc00 	lsr	x0, x0, #32
  400874:	13027c02 	asr	w2, w0, #2
  400878:	131f7c20 	asr	w0, w1, #31
  40087c:	4b000042 	sub	w2, w2, w0
  400880:	2a0203e0 	mov	w0, w2
  400884:	531e7400 	lsl	w0, w0, #2
  400888:	0b020000 	add	w0, w0, w2
  40088c:	531f7800 	lsl	w0, w0, #1
  400890:	4b000020 	sub	w0, w1, w0
  400894:	b9034fa0 	str	w0, [x29, #844]
  400898:	b9035bbf 	str	wzr, [x29, #856]
  40089c:	14000020 	b	40091c <sort2+0x128>
  4008a0:	b9835ba2 	ldrsw	x2, [x29, #856]
  4008a4:	b9834fa1 	ldrsw	x1, [x29, #844]
  4008a8:	aa0103e0 	mov	x0, x1
  4008ac:	d37ef400 	lsl	x0, x0, #2
  4008b0:	8b010000 	add	x0, x0, x1
  4008b4:	d37ef400 	lsl	x0, x0, #2
  4008b8:	8b020000 	add	x0, x0, x2
  4008bc:	d37ef400 	lsl	x0, x0, #2
  4008c0:	9100a3a1 	add	x1, x29, #0x28
  4008c4:	b8606820 	ldr	w0, [x1, x0]
  4008c8:	7100001f 	cmp	w0, #0x0
  4008cc:	54000221 	b.ne	400910 <sort2+0x11c>  // b.any
  4008d0:	b9835fa0 	ldrsw	x0, [x29, #860]
  4008d4:	d37ef400 	lsl	x0, x0, #2
  4008d8:	f9400fa1 	ldr	x1, [x29, #24]
  4008dc:	8b000020 	add	x0, x1, x0
  4008e0:	b9400002 	ldr	w2, [x0]
  4008e4:	b9835ba3 	ldrsw	x3, [x29, #856]
  4008e8:	b9834fa1 	ldrsw	x1, [x29, #844]
  4008ec:	aa0103e0 	mov	x0, x1
  4008f0:	d37ef400 	lsl	x0, x0, #2
  4008f4:	8b010000 	add	x0, x0, x1
  4008f8:	d37ef400 	lsl	x0, x0, #2
  4008fc:	8b030000 	add	x0, x0, x3
  400900:	d37ef400 	lsl	x0, x0, #2
  400904:	9100a3a1 	add	x1, x29, #0x28
  400908:	b8206822 	str	w2, [x1, x0]
  40090c:	14000007 	b	400928 <sort2+0x134>
  400910:	b9435ba0 	ldr	w0, [x29, #856]
  400914:	11000400 	add	w0, w0, #0x1
  400918:	b9035ba0 	str	w0, [x29, #856]
  40091c:	b9435ba0 	ldr	w0, [x29, #856]
  400920:	71004c1f 	cmp	w0, #0x13
  400924:	54fffbed 	b.le	4008a0 <sort2+0xac>
  400928:	b9435fa0 	ldr	w0, [x29, #860]
  40092c:	11000400 	add	w0, w0, #0x1
  400930:	b9035fa0 	str	w0, [x29, #860]
  400934:	b9435fa1 	ldr	w1, [x29, #860]
  400938:	b94017a0 	ldr	w0, [x29, #20]
  40093c:	6b00003f 	cmp	w1, w0
  400940:	54fff84b 	b.lt	400848 <sort2+0x54>  // b.tstop
  400944:	b90357bf 	str	wzr, [x29, #852]
  400948:	b9035fbf 	str	wzr, [x29, #860]
  40094c:	14000034 	b	400a1c <sort2+0x228>
  400950:	b9035bbf 	str	wzr, [x29, #856]
  400954:	1400002c 	b	400a04 <sort2+0x210>
  400958:	b9835ba2 	ldrsw	x2, [x29, #856]
  40095c:	b9835fa1 	ldrsw	x1, [x29, #860]
  400960:	aa0103e0 	mov	x0, x1
  400964:	d37ef400 	lsl	x0, x0, #2
  400968:	8b010000 	add	x0, x0, x1
  40096c:	d37ef400 	lsl	x0, x0, #2
  400970:	8b020000 	add	x0, x0, x2
  400974:	d37ef400 	lsl	x0, x0, #2
  400978:	9100a3a1 	add	x1, x29, #0x28
  40097c:	b8606820 	ldr	w0, [x1, x0]
  400980:	7100001f 	cmp	w0, #0x0
  400984:	540003a0 	b.eq	4009f8 <sort2+0x204>  // b.none
  400988:	b98357a0 	ldrsw	x0, [x29, #852]
  40098c:	d37ef400 	lsl	x0, x0, #2
  400990:	f9400fa1 	ldr	x1, [x29, #24]
  400994:	8b000022 	add	x2, x1, x0
  400998:	b9835ba3 	ldrsw	x3, [x29, #856]
  40099c:	b9835fa1 	ldrsw	x1, [x29, #860]
  4009a0:	aa0103e0 	mov	x0, x1
  4009a4:	d37ef400 	lsl	x0, x0, #2
  4009a8:	8b010000 	add	x0, x0, x1
  4009ac:	d37ef400 	lsl	x0, x0, #2
  4009b0:	8b030000 	add	x0, x0, x3
  4009b4:	d37ef400 	lsl	x0, x0, #2
  4009b8:	9100a3a1 	add	x1, x29, #0x28
  4009bc:	b8606820 	ldr	w0, [x1, x0]
  4009c0:	b9000040 	str	w0, [x2]
  4009c4:	b9835ba2 	ldrsw	x2, [x29, #856]
  4009c8:	b9835fa1 	ldrsw	x1, [x29, #860]
  4009cc:	aa0103e0 	mov	x0, x1
  4009d0:	d37ef400 	lsl	x0, x0, #2
  4009d4:	8b010000 	add	x0, x0, x1
  4009d8:	d37ef400 	lsl	x0, x0, #2
  4009dc:	8b020000 	add	x0, x0, x2
  4009e0:	d37ef400 	lsl	x0, x0, #2
  4009e4:	9100a3a1 	add	x1, x29, #0x28
  4009e8:	b820683f 	str	wzr, [x1, x0]
  4009ec:	b94357a0 	ldr	w0, [x29, #852]
  4009f0:	11000400 	add	w0, w0, #0x1
  4009f4:	b90357a0 	str	w0, [x29, #852]
  4009f8:	b9435ba0 	ldr	w0, [x29, #856]
  4009fc:	11000400 	add	w0, w0, #0x1
  400a00:	b9035ba0 	str	w0, [x29, #856]
  400a04:	b9435ba0 	ldr	w0, [x29, #856]
  400a08:	71004c1f 	cmp	w0, #0x13
  400a0c:	54fffa6d 	b.le	400958 <sort2+0x164>
  400a10:	b9435fa0 	ldr	w0, [x29, #860]
  400a14:	11000400 	add	w0, w0, #0x1
  400a18:	b9035fa0 	str	w0, [x29, #860]
  400a1c:	b9435fa0 	ldr	w0, [x29, #860]
  400a20:	7100241f 	cmp	w0, #0x9
  400a24:	54fff96d 	b.le	400950 <sort2+0x15c>
  400a28:	d503201f 	nop
  400a2c:	a9407bfd 	ldp	x29, x30, [sp]
  400a30:	910d83ff 	add	sp, sp, #0x360
  400a34:	d65f03c0 	ret

0000000000400a38 <bucketSort3>:
  400a38:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400a3c:	910003fd 	mov	x29, sp
  400a40:	f9000fa0 	str	x0, [x29, #24]
  400a44:	b90017a1 	str	w1, [x29, #20]
  400a48:	b94017a1 	ldr	w1, [x29, #20]
  400a4c:	f9400fa0 	ldr	x0, [x29, #24]
  400a50:	97ffff4b 	bl	40077c <findMaxNum>
  400a54:	b9002ba0 	str	w0, [x29, #40]
  400a58:	b9402ba0 	ldr	w0, [x29, #40]
  400a5c:	97ffff28 	bl	4006fc <getLoopTimes>
  400a60:	b90027a0 	str	w0, [x29, #36]
  400a64:	52800020 	mov	w0, #0x1                   	// #1
  400a68:	b9002fa0 	str	w0, [x29, #44]
  400a6c:	14000008 	b	400a8c <bucketSort3+0x54>
  400a70:	b9402fa2 	ldr	w2, [x29, #44]
  400a74:	b94017a1 	ldr	w1, [x29, #20]
  400a78:	f9400fa0 	ldr	x0, [x29, #24]
  400a7c:	97ffff5e 	bl	4007f4 <sort2>
  400a80:	b9402fa0 	ldr	w0, [x29, #44]
  400a84:	11000400 	add	w0, w0, #0x1
  400a88:	b9002fa0 	str	w0, [x29, #44]
  400a8c:	b9402fa1 	ldr	w1, [x29, #44]
  400a90:	b94027a0 	ldr	w0, [x29, #36]
  400a94:	6b00003f 	cmp	w1, w0
  400a98:	54fffecd 	b.le	400a70 <bucketSort3+0x38>
  400a9c:	d503201f 	nop
  400aa0:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400aa4:	d65f03c0 	ret

0000000000400aa8 <main>:
  400aa8:	a9bb7bfd 	stp	x29, x30, [sp, #-80]!
  400aac:	910003fd 	mov	x29, sp
  400ab0:	90000000 	adrp	x0, 400000 <_init-0x558>
  400ab4:	91302001 	add	x1, x0, #0xc08
  400ab8:	910043a0 	add	x0, x29, #0x10
  400abc:	a9400c22 	ldp	x2, x3, [x1]
  400ac0:	a9000c02 	stp	x2, x3, [x0]
  400ac4:	a9410c22 	ldp	x2, x3, [x1, #16]
  400ac8:	a9010c02 	stp	x2, x3, [x0, #16]
  400acc:	f9401022 	ldr	x2, [x1, #32]
  400ad0:	f9001002 	str	x2, [x0, #32]
  400ad4:	b9402821 	ldr	w1, [x1, #40]
  400ad8:	b9002801 	str	w1, [x0, #40]
  400adc:	910043a0 	add	x0, x29, #0x10
  400ae0:	f90023a0 	str	x0, [x29, #64]
  400ae4:	52800160 	mov	w0, #0xb                   	// #11
  400ae8:	b9003fa0 	str	w0, [x29, #60]
  400aec:	b9403fa1 	ldr	w1, [x29, #60]
  400af0:	f94023a0 	ldr	x0, [x29, #64]
  400af4:	97ffffd1 	bl	400a38 <bucketSort3>
  400af8:	b9004fbf 	str	wzr, [x29, #76]
  400afc:	1400000b 	b	400b28 <main+0x80>
  400b00:	b9804fa0 	ldrsw	x0, [x29, #76]
  400b04:	d37ef400 	lsl	x0, x0, #2
  400b08:	910043a1 	add	x1, x29, #0x10
  400b0c:	b8606821 	ldr	w1, [x1, x0]
  400b10:	90000000 	adrp	x0, 400000 <_init-0x558>
  400b14:	91300000 	add	x0, x0, #0xc00
  400b18:	97fffeb2 	bl	4005e0 <printf@plt>
  400b1c:	b9404fa0 	ldr	w0, [x29, #76]
  400b20:	11000400 	add	w0, w0, #0x1
  400b24:	b9004fa0 	str	w0, [x29, #76]
  400b28:	b9404fa1 	ldr	w1, [x29, #76]
  400b2c:	b9403fa0 	ldr	w0, [x29, #60]
  400b30:	6b00003f 	cmp	w1, w0
  400b34:	54fffe6b 	b.lt	400b00 <main+0x58>  // b.tstop
  400b38:	52800140 	mov	w0, #0xa                   	// #10
  400b3c:	97fffead 	bl	4005f0 <putchar@plt>
  400b40:	52800000 	mov	w0, #0x0                   	// #0
  400b44:	a8c57bfd 	ldp	x29, x30, [sp], #80
  400b48:	d65f03c0 	ret
  400b4c:	00000000 	.inst	0x00000000 ; undefined

0000000000400b50 <__libc_csu_init>:
  400b50:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400b54:	910003fd 	mov	x29, sp
  400b58:	a901d7f4 	stp	x20, x21, [sp, #24]
  400b5c:	90000094 	adrp	x20, 410000 <__FRAME_END__+0xf3cc>
  400b60:	90000095 	adrp	x21, 410000 <__FRAME_END__+0xf3cc>
  400b64:	91374294 	add	x20, x20, #0xdd0
  400b68:	913722b5 	add	x21, x21, #0xdc8
  400b6c:	a902dff6 	stp	x22, x23, [sp, #40]
  400b70:	cb150294 	sub	x20, x20, x21
  400b74:	f9001ff8 	str	x24, [sp, #56]
  400b78:	2a0003f6 	mov	w22, w0
  400b7c:	aa0103f7 	mov	x23, x1
  400b80:	9343fe94 	asr	x20, x20, #3
  400b84:	aa0203f8 	mov	x24, x2
  400b88:	97fffe74 	bl	400558 <_init>
  400b8c:	b4000194 	cbz	x20, 400bbc <__libc_csu_init+0x6c>
  400b90:	f9000bb3 	str	x19, [x29, #16]
  400b94:	d2800013 	mov	x19, #0x0                   	// #0
  400b98:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400b9c:	aa1803e2 	mov	x2, x24
  400ba0:	aa1703e1 	mov	x1, x23
  400ba4:	2a1603e0 	mov	w0, w22
  400ba8:	91000673 	add	x19, x19, #0x1
  400bac:	d63f0060 	blr	x3
  400bb0:	eb13029f 	cmp	x20, x19
  400bb4:	54ffff21 	b.ne	400b98 <__libc_csu_init+0x48>  // b.any
  400bb8:	f9400bb3 	ldr	x19, [x29, #16]
  400bbc:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400bc0:	a942dff6 	ldp	x22, x23, [sp, #40]
  400bc4:	f9401ff8 	ldr	x24, [sp, #56]
  400bc8:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400bcc:	d65f03c0 	ret

0000000000400bd0 <__libc_csu_fini>:
  400bd0:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400bd4 <_fini>:
  400bd4:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400bd8:	910003fd 	mov	x29, sp
  400bdc:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400be0:	d65f03c0 	ret
